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Cypress Semiconductor /psoc63 /USBFS0 /USBHOST /HOST_CTL2

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Interpret as HOST_CTL2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RETRY)RETRY 0 (CANCEL)CANCEL 0 (SOFSTEP)SOFSTEP 0 (ALIVE)ALIVE 0 (RSVD_4)RSVD_4 0 (RSVD_5)RSVD_5 0TTEST

Description

Host Control 2 Register.

Fields

RETRY

If this bit is set to ‘1’, the target token is retried if a NAK or error* occurs. Retry processing is performed during the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER).

  • : HOST_ERR.RERR=‘1’, HOST_ERR.TOUT=‘1’, HOST_ERR.CRC=‘1’, HOST_ERR.TGERR=‘1’, HOST_ERR.STUFF=‘1’ ‘0’ : Doesn’t retry token sending. ‘1’ : Retries token sending Note:
  • This bit isn’t initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to ‘1’.
CANCEL

When this bit is set to ‘1’, if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to ‘0’, token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST). ‘0’ : Continues a token. ‘1’ : Cancels a token.
SOFSTEP

If this bit is set to ‘1’, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to ‘1’ each time SOF is sent. If this bit is set to ‘0’, the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to ‘1’. ‘0’ : An interrupt occurred due to the HOST_HFCOMP setting. ‘1’ : An interrupt occurred. Notes:

  • If a SOF token (TKNEN=‘001’) is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to ‘1’ regardless of the setting of this bit.
ALIVE

This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to ‘1’ while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is ‘0’, SE0 is output instead of SOF. This bit is effective when the CLKSEL bit of the Host Conrtol 1 Register (HOST_CTL1) is ‘0’. If the CLKSEL bit is ‘1’, SOF is output regardless of the setting of the ALIVE bit. ‘0’ : SOF output. ‘1’ : SE0 output (Keep alive)
RSVD_4

N/A
RSVD_5

N/A
TTEST

Timer Test. Set this bits to ‘00’.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data